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The traditional category X GM tournament in Lippstadt (Germany) has an illustrious field of players from all over the world. This year the FPGA program Brutus, developed by Dr Christian Donninger of Austria. The acronym "FPGA" stands for Field Programmable Gate Arrays and is essentially a programmable chip. Donninger has written chess playing code for FPGA, which will run very much faster than on a general purpose chip like the Pentium or Athlon. The University of Paderborn has joined in to parallelise the system.
An
early version of the Brutus development card
An additional benefit of using FPGAs is that it is not just the search routines
that are speeded up dramatically. Due to the sturcture of the code you can add
chess knowledge in any quantity without slowing down the process. In regular
PC programs each new quantum of knowledge is expensive – it is bought at
the price of search speed. The FPGA program does not slow down when you add
new knowledge modules.
Romanishin,O (2561) – BrutusP-I.XII [E07]
11th GM Lippstadt (1), 07.08.2003
21...Bxf2!? Brutus simply cannot resist such motifs, it is vicious about attacking the enemy king. Here the hardware program has seen that it will get a permanent attack and between two and four pawns for the piece.
The game continued 22.Kxf2 Nfg4+ 23.Kg1 Qh6 24.Rc3 Qxh2+ 25.Kf1 h5! 26.Qd4 h4 27.gxh4 Qxh4 28.Rh3 Nh2+ 29.Kg1? (Zeitnot) 29...Nhf3+ 30.Bxf3 Qxh3 31.Nd2 and White resigned because of 31...Nxf3+ 32.Nxf3 Qg3+ 33.Kf1 Qxf3+. 0-1.
The hardware in Lippstadt was supplied by Alpha Data Parallel Systems Ltd. and the University of Paderborn. Dr Donninger's project is funded by ChessBase.
